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On Windows 7, select Start > All Programs > Xilinx Design Tools > Vivado 2013.2 > Vivado 2013.2.

Steps for building the FPGA hardware bitstream

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This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool and how to export the hardware platform to Xilinx Software Development Kit (SDK) for software application development. Set ZYNQ_QT_INSTALL environment variable by referring to Xilinx Zynq Qt/Qwt Libraries - Build Instructions

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A Linux development PC with QT and QWT libraries cross-compiled for Zynq platform.

For more information, refer to Xilinx Petalinux user manuals.

A Linux development PC with Petalinux SDK installed.

For more information, refer to the Xilinx Git wiki and to UG821: Xilinx Zynq-7000 SoC Software Developers Guide.

A Linux development PC with the distributed version control system Git installed.

The ARM GNU tools are included with the Xilinx ISE Design Suite Embedded Edition or can be downloaded separately.

A Linux development PC with the ARM GNU tools installed.

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The pre-built bitfile and boot images are built from a full logiCVC IP core and don't expire. Note: The provided logiCVC evaluation IP core has a 1 hour timeout built-in such that the display freezes after the timer expires. License options are listed on the Xylon logiCVC-ML product site.

Xylon logiCVC-ML is shipped as evaluation IP core that does not require a license.

Xilinx IP evaluation licenses for the Video Timing Controller and Chroma Resampler IP cores can be ordered online.

A 30-day evaluation license can be generated after registering a Xilinx account. For additional information, refer to UG798 ISE Design Suite 14: Installation and Licensing Guide.

The ZC702 Evaluation Kit ships with the Xilinx Vivadoв„ў Design Suite version 2013.2 Device-locked to the Zynq-7000 XC7Z020 CLG484-1 device and all required licenses to build the TRD.

This wiki page assumes the user has already downloaded the Base TRD package and extracted its contents to the Base TRD home directory referred to as ZYNQ_TRD_HOME in this wiki. It also includes the binaries necessary to configure and boot the Zynq-7000 SoC board.

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For additional information, please refer to UG925: Zynq-7000 SoC: ZC702 Base Targeted Reference Design User Guide.ДЄn archive with the TRD files can be downloaded here (requires to sign up).ДЎ.3 Base TRD Package Contents The Zynq Base TRD package is released with the source code, Xilinx Vivado and SDK projects, and an SD card image that enables the user to run the video demonstration and software application. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications. The Base TRD demonstrates how the user can seamlessly switch between a software or a hardware implementation and evaluate the cost and benefit of each implementation. The SoC allows the user to implement a video processing algorithm that performs edge detection on an image (Sobel filter) either as a software program running on the Zynq-7000 SoC based PS or as a hardware accelerator inside the SoC based PL. The Base TRD consists of two elements: The Zynq-7000 SoC Processing System (PS) and a video processing pipeline implemented in Programmable Logic (PL). The Base TRD is an embedded video processing application designed to showcase various features and capabilities of the Zynq Z-7020 SoC device for the embedded domain. For additional information, refer to Zynq-7000 SoC: ZC702 Evaluation Kit and Video and Imaging Kit Getting Started Guide. The ZC702 Evaluation kit is based on a XC7Z020 CLG484-1 Zynq-7000 SoC device. This page provides instructions on how to build various components of the Zynq Base Targeted Reference Design (TRD) and how to setup the hardware platform and run the design on the ZC702 Evaluation Kit.

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